module Light_Module
 (
    input                  clk ,
	 input                  rstn,
	 input                  light_mask,  //1:输出lightcode码   0：输出0码
	 input   [127:0]        lightCode,
	 
	 input                  bit_clk,
	 input                  frame_clk,
	 output reg             light_out
 );

	reg [3:0]         hi_cnt;
	reg [3:0]         hi_cnt_up; 
   //-------------------------------------------
	//-- 描述：RZ码输出
	//-------------------------------------------
	reg[7:0] bit_pos=8'd0;
	
   always@(posedge clk or negedge rstn)
   begin
	  if(rstn==1'b0)
	    bit_pos <= 127;
	  else
	    begin
	      if(frame_clk) 
			  bit_pos <= 127;
			else if(bit_clk)
			  bit_pos <= bit_pos-1;
		 end
   end
	
	always@(posedge clk or negedge rstn)
   begin
	  if(rstn==1'b0)
	    hi_cnt <= 4'd3;
	  else if(bit_clk)
	    begin
	      if((lightCode[bit_pos])&&(light_mask==1'b1)) 
			  hi_cnt <= 4'd7;
			else
			  hi_cnt <= 4'd3;
		 end
   end
	
	always@(posedge clk or negedge rstn)
   begin
	  if(rstn==1'b0)
	    begin
	      hi_cnt_up <= 4'd0;
			light_out <= 1'b0;
		 end
	  else 
	    begin
	      if(bit_clk)
		     begin	
			    hi_cnt_up <= 4'd1;
				 light_out <= 1'b0;
			  end
			else if(hi_cnt_up<=hi_cnt)
			  begin
			    hi_cnt_up <= hi_cnt_up + 1'b1;
				 light_out <= 1'b1;
			  end
			else
			  begin
			    hi_cnt_up <= hi_cnt_up;
				 light_out <= 1'b0;
			  end
		 end
   end
	
	
endmodule 